1. Technical Field
Example embodiments relate generally to a semiconductor memory device. More particularly, embodiments of the present inventive concept relate to a power loss test technique for a non-volatile memory device (e.g., a flash memory device, etc).
2. Description of the Related Art
A semiconductor memory device may be classified into two types (i.e., a volatile memory device and a non-volatile memory device) according to whether data can be retained when power is not supplied. Recently, a NAND flash memory device is widely used as the non-volatile memory device because the NAND flash memory device can be manufactured smaller in size while having higher capacity. Thus, a storage device including the NAND flash memory device (e.g., an embedded multi media card (eMMC), a solid state drive (SSD), etc) has been replacing a hard disk drive (HDD). Generally, the NAND flash memory device includes at least one NAND flash memory and a memory controller that controls the NAND flash memory. Specifically, the memory controller performs an address mapping operation based on a flash translation layer (FTL) for supporting a file system. In addition, the memory controller controls, for the NAND flash memory, a read operation, a write operation, an erase operation, a merge operation, a copy-back operation, a compaction operation, a garbage collection operation, a wear leveling operation, and the like.
As described above, many operations, which a host device does not recognize, are performed in the non-volatile memory device. Thus, if a sudden power-off occurs (i.e., if power supplied to the non-volatile memory device is suddenly cut off while the non-volatile memory device performs the write operation or the garbage collection operation), data and/or meta-data related thereto may be lost, so that an error (i.e., a malfunction) of the non-volatile memory device may be caused. Accordingly, in order to achieve reliability-in use, the non-volatile memory device is required to prevent the error due to losses of the data and/or the meta-data by performing a data recovery operation when the sudden power-off occurs. Typically, a reliability-in use-test responding to the sudden power-off (i.e., referred to as a power loss test) is performed for the non-volatile memory device before shipping the non-volatile memory device. A conventional test technique checks whether an error due to losses of data and/or meta-data related thereto occurs by randomly cutting off power supplied to a non-volatile memory device while the non-volatile memory device performs a write operation. However, since the conventional test technique randomly cuts off the power while the non-volatile memory device performs the write operation, the conventional test technique cannot consider an internal operating state of the non-volatile memory device. In other words, the conventional test technique inefficiently performs the power loss test.